WHEN REG IS NOT A FLIP FLOP in Verilog.

Презентація - інтервю для ABB.

WHEN REG IS NOT A FLIP FLOP in Verilog.

Used information:

[1]https://www.researchgate.net/post/Again_what_is_the_difference_between_wire_and_reg_in_Verilog

[2] http://web.mit.edu/6.111/www/f2007/handouts/L06.pdf

[3] https://courses.cs.washington.edu/courses/cse370/10wi/pdfs/lectures/15-SeqVerilog.pdf

In my work experience and are lot of time which I spent on interview I heard this questions or close to him many times. So let see how it is worked.

As we know reg is a verilog data type that can be synthesized into either sequential or combinational logic depending on how you code it.

So lets reviewed all kinds of organization code. Also we know reg is used inside

always @( ), and inside brackets we can use two kinds organization , in first use (posedge clk ) or (negedge clk )  for sequential logic (flip-flop), and second is (*) or (clk) or (some input signal or wire) or (signal_1 or signal_2 or signal_3). And inside body of always @( ) which market begin  end. For reg assignments we can use (=)blocking and (<=)non-blocking assignment , in the next example we used (posedge clk) and non-blocking assignment.

for example

reg myreg;

always @ (posedge clk) begin
  myreg <= some_input;
end

Assumed this all kinds we can write four different code combinations :

1.1 In first code example myreg_1... will be synthesize in FLIP-FLOPs as you can see in Image 1, also I provided  compilation report information from Xilinx ISE WEB pack Tool.

reg myreg_1, myreg_2, myreg_3;

always @ (posedge clk) begin // or (negedge clk)
  myreg_1 <= some_input;

  myreg_2 <= some_input;

  myreg_3 <= some_input;
end

 Image 1

============================================================

*                           HDL Synthesis                               *

============================================================

Performing bidirectional port resolution...

Synthesizing Unit <test_code>.

    Related source file is "test_code.v".

    Register <myreg_2> equivalent to <myreg_1> has been removed

    Register <myreg_3> equivalent to <myreg_1> has been removed

    Found 1-bit register for signal <myreg_1>.

    Summary:

                inferred   1 D-type flip-flop(s).

Unit <test_code> synthesized.

============================================================

HDL Synthesis Report

Macro Statistics

# Registers                                            : 1

 1-bit register                                        : 1

============================================================

============================================================

HDL Synthesis Report

Macro Statistics

# Registers                                            : 1

 1-bit register                                        : 1

============================================================

============================================================

*                         Low Level Synthesis                           *

============================================================

Optimizing unit <test_code> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block test_code, actual ratio is 0.

FlipFlop myreg_1 has been replicated 2 time(s) to handle iob=true attribute.

Final Macro Processing ...

============================================================

Final Register Report

Macro Statistics

# Registers                                            : 3

 Flip-Flops                                            : 3

============================================================

1.2 This kind of code showing how FLIP-FLOP will be connected when we use assignment result for other assignment Image 2. And this kind of assignment classical used in design pipeline design or shift registers design.

reg myreg_1, myreg_2, myreg_3;

always @ (posedge clk) begin // or (negedge clk)
  myreg_1 <= some_input;

  myreg_2 <= myreg_1;

  myreg_3 <= myreg_2;
end

Image 2.

============================================================

*                           HDL Synthesis                               *

============================================================

Performing bidirectional port resolution...

Synthesizing Unit <test_code>.

    Related source file is "test_code.v".

    Found 1-bit register for signal <myreg_1>.

    Found 1-bit register for signal <myreg_2>.

    Found 1-bit register for signal <myreg_3>.

    Summary:

                inferred   3 D-type flip-flop(s).

Unit <test_code> synthesized.

============================================================

HDL Synthesis Report

Macro Statistics

# Registers                                            : 3

 1-bit register                                        : 3

============================================================

============================================================

*                       Advanced HDL Synthesis                          *

============================================================

============================================================

Advanced HDL Synthesis Report

Macro Statistics

# Registers                                            : 3

 Flip-Flops                                            : 3

============================================================

============================================================

*                         Low Level Synthesis                           *

============================================================

Optimizing unit <test_code> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block test_code, actual ratio is 0.

FlipFlop myreg_1 has been replicated 1 time(s) to handle iob=true attribute.

Final Macro Processing ...

Processing Unit <test_code> :

                Found 2-bit shift register for signal <myreg_2>.

Unit <test_code> processed.

============================================================

Final Register Report

Macro Statistics

# Registers                                            : 2

 Flip-Flops                                            : 2

# Shift Registers                                      : 1

 2-bit shift register                                  : 1

============================================================

2. This part of code also will be synthesize in FLIP-FLOP logic

reg myreg_1, myreg_2, myreg_3;

always @ (posedge clk) begin // or (negedge clk)
  myreg_1 = some_input;
  myreg_2 = myreg_1;

  myreg_3 = myreg_2;

end

Image 3

============================================================

*                           HDL Synthesis                               *

============================================================

Performing bidirectional port resolution...

Synthesizing Unit <test_code>.

    Related source file is "test_code.v".

    Register <myreg_2> equivalent to <myreg_1> has been removed

    Register <myreg_3> equivalent to <myreg_1> has been removed

    Found 1-bit register for signal <myreg_1>.

    Summary:

                inferred   1 D-type flip-flop(s).

Unit <test_code> synthesized.

============================================================

HDL Synthesis Report

Macro Statistics

# Registers                                            : 1

 1-bit register                                        : 1

============================================================

============================================================

*                       Advanced HDL Synthesis                          *

============================================================

============================================================

Advanced HDL Synthesis Report

Macro Statistics

# Registers                                            : 1

 Flip-Flops                                            : 1

============================================================

============================================================

*                         Low Level Synthesis                           *

============================================================

Optimizing unit <test_code> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block test_code, actual ratio is 0.

FlipFlop myreg_1 has been replicated 2 time(s) to handle iob=true attribute.

Final Macro Processing ...

============================================================

Final Register Report

Macro Statistics

# Registers                                            : 3

 Flip-Flops                                            : 3

============================================================

3.This kind of code will be synthesize  in Combinational Logic !!! Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic.!!! Not recommend to use .

always @( some_input) // or (*)or (clk) or (signal_1 or signal_2 or signal_3)

begin

if (some_input == 1'b1)

begin

myreg_1 <= 1'b0;

myreg_2 <= myreg_1 & some_input;

myreg_3 <= myreg_2 | myreg_1;

end

else

begin

myreg_1 <= 1'b1;

myreg_2 <= myreg_1 | some_input;

myreg_3 <= myreg_2 & myreg_1;

end

end

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling verilog file "test_code.v" in library work

Module <test_code> compiled

No errors in compilation

Analysis of file <"test_code.prj"> succeeded.

=========================================================================

*                     Design Hierarchy Analysis                         *

=========================================================================

Analyzing hierarchy for module <test_code> in library <work>.

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing top module <test_code>.

Module <test_code> is correct for synthesis.

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <test_code>.

    Related source file is "test_code.v".

WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Unit <test_code> synthesized.

=========================================================================

HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

*                       Advanced HDL Synthesis                          *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

*                         Low Level Synthesis                           *

=========================================================================

Optimizing unit <test_code> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block test_code, actual ratio is 0.

Final Macro Processing ...

=========================================================================

Final Register Report

Found no macro

=========================================================================

4. This kind of code will be also synthesize  in Combinational Logic and recommend to use. !!! Guideline: use blocking assignments for combinational always blocks. !!!

always @( some_input) // or (*) or (clk) or (signal_1 or signal_2 or signal_3)

begin

if (some_input == 1'b1)

begin

myreg_1 = 1'b0;

myreg_2 = myreg_1 & some_input;

myreg_3 = myreg_2 | myreg_1;

end

else

begin

myreg_1 = 1'b1;

myreg_2 = myreg_1 | some_input;

myreg_3 = myreg_2 & myreg_1;

end
end

Traffic light on Verilog.

Використанні матеріали.
http://www.lbebooks.com/downloads/exportal/verilog_basys_example62-trafficlights.pdf

Всім привіт. Вирішив написати цей пост коли проходив тестування в Intel, і завдання було написання модулю світлофора , з можливістю налаштування його роботи.

Єдиною вхідною інформацією, була вхідна частота блоку 10МГц ось і все.

Проект складається з таких модулів:

- traffic_top.v ;

- traffic_fsm.v;

- clk_divider_1_s;

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Zazulyak Yaroslav
//////////////////////////////////////////////////////////////////////////////////
module traffic_top(
    input clk_10_Mhz,
input direction,
input enable,
input clr,
output green,
output yellow,
output red,
output test_clk_1_s,
output [4:0]test_state
);
// wires
wire red_w, yellow_w, green_w;
wire clk_10_Mhz_w;
wire clk_1_s_w;
wire direction_w;
wire enable_w;
wire [4:0] test_state_w;

// moduls
clk_divider_1_s U1
(
.clk_10_Mhz(clk_10_Mhz_w),
//.clr(clr),
.clk_1_s(clk_1_s_w)
);

traffic_fsm U2
(
.clk(clk_1_s_w),
.clr(clr),
.direction(direction_w),
.enable(enable_w),
.red(red_w),
.green(green_w),
.yellow(yellow_w),
.test_state(test_state_w)
);

assign clk_10_Mhz_w = clk_10_Mhz;
assign direction_w = direction;

assign enable_w = enable;
assign red = red_w;
assign yellow = yellow_w;
assign green = green_w ;
assign test_state  = test_state_w;
assign test_clk_1_s = clk_1_s_w;

endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Zazulyak Yaroslav
//////////////////////////////////////////////////////////////////////////////////
module traffic_fsm(
    input clk,
input clr,
input direction, // if "0"  then direction  North-South, else "1" direction East-West
input enable,
output red,
output green,
output yellow,
// test
output [4:0]test_state
);


reg [4:0] state;
reg [2:0] ligths;
reg [7:0] count;

parameter SET_ONE  = 1'b1;
parameter SET_ZERO = 1'b0;
//states
parameter IDLE_st = 5'b00000,
GREEN_st    = 5'b00001, YELLOW_1_st = 5'b00010 , RED_1_st = 5'b00100,  // North-South
RED_2_st    = 5'b01000, YELLOW_2_st = 5'b10000; // East-West

parameter GREEN_delay = 8'b00000101  , YELLOW_delay = 8'b00000010  , RED_delay = 8'b00000001 ,
TOTAL_delay = GREEN_delay + YELLOW_delay + RED_delay ;
initial
 begin
state  = IDLE_st;
ligths = 0;
count  = 8'b0000000;
 end

// sequential logic

always @( posedge clk  )
begin
if ( clr == SET_ONE )
begin
state <= IDLE_st;
count <= 0;
end
else

case(state)
IDLE_st : if ( direction == SET_ZERO && enable == SET_ONE)
begin
state <= GREEN_st; // North-South
count <= 0;
end
else if (direction == SET_ONE && enable == SET_ONE)
begin
state <= RED_2_st; // East-West
count <= 0;
end
else //(enable == SET_ZERO)
begin
state <= IDLE_st;
count <= 0;
end

GREEN_st : if ( state == GREEN_st && count == GREEN_delay - 1'b1 ) // North-South
begin
state <= YELLOW_1_st;
count <= 0;
end
else
begin
state <= GREEN_st;
count <= count + 1;
end

YELLOW_1_st : if (state == YELLOW_1_st && count == YELLOW_delay - 1'b1)
begin
state <= RED_1_st;
count <= 0;
end
else
begin
state <= YELLOW_1_st;
count <= count + 1;
end
RED_1_st : if (state == RED_1_st && count == RED_delay - 1'b1 && enable == SET_ONE)
begin
state <= RED_2_st;
count <= 0;
end
else if (state == RED_1_st && count == RED_delay - 1'b1 && enable == SET_ZERO)
begin
state <= IDLE_st;
count <= 0;
end
else
begin
state <= RED_1_st;
count <= count + 1;
end
RED_2_st   : if (state == RED_2_st && count == TOTAL_delay - 1'b1) // East-West
begin
state <= YELLOW_2_st;
count <= 0;
end
else
begin
state <= RED_2_st;
count <= count + 1;
end
YELLOW_2_st : if (state == YELLOW_2_st && count == YELLOW_delay - 1'b1 &&  enable == SET_ONE)
begin
state <= GREEN_st;
count <= 0;
end
else if (state == YELLOW_2_st && count == YELLOW_delay - 1'b1 && enable == SET_ZERO)
begin
state <= IDLE_st;
count <= 0;
end
else
begin
state <= YELLOW_2_st;
count <= count + 1;
end
default :
begin
state <= IDLE_st;
count <= 0;
end
endcase

end
// end sequential logic


// combinational logic
always @(*)
begin
case (state)
IDLE_st : ligths = 3'b000;
GREEN_st : ligths = 3'b001; // North-South
YELLOW_1_st : ligths = 3'b010;
RED_1_st : ligths = 3'b100;
RED_2_st : ligths = 3'b100; // East-West
YELLOW_2_st : ligths = 3'b010;
default : ligths = 3'b000;
endcase
end


assign red =  ligths[2];
assign yellow =  ligths[1];
assign green =  ligths[0];
// end combinational logic

//
assign test_state = state;


endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Engineer: Zazulyak Yaroslav

//////////////////////////////////////////////////////////////////////////////////

module clk_divider_1_s(

input clk_10_Mhz,

//input clr  ,

output   clk_1_s    // output with 1 second period 

    );

reg [22:0] q_reg;

reg clk_out;

parameter SET_ONE  = 1'b1;

parameter SET_ZERO = 1'b0;

initial 

begin

q_reg   = 0;

clk_out = 0;

end

always @(posedge clk_10_Mhz)

begin

//if (clr == SET_ONE)

// q_reg <= 0;

//else

if ( q_reg == 23'b10011000100101100111111) // every 4 999 999 pulses (0,5 second) invert clk_out ( T = 1 s)

begin

q_reg <= 0;

clk_out <= ~clk_out;

end

else 

q_reg <= q_reg + 1;

end

assign clk_1_s = clk_out;

endmodule

+ DUT модуль для тестування(симуляції) всього проекту

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Engineer: Zazulyak Yaroslav

////////////////////////////////////////////////////////////////////////////////

module sim_traffic;

// Inputs

reg clk_10_Mhz;

reg direction;

reg enable;

reg clr;

// Outputs

wire green;

wire yellow;

wire red;

wire test_clk_1_s;

wire [4:0] test_state;

// Instantiate the Unit Under Test (UUT)

traffic_top uut (

.clk_10_Mhz(clk_10_Mhz), 

.direction(direction), 

.enable(enable), 

.clr(clr), 

.green(green), 

.yellow(yellow), 

.red(red),

.test_clk_1_s(test_clk_1_s),

.test_state(test_state)

);

parameter half_period = 50;

parameter one_second  = 10000000 * (half_period * 2);

initial begin

// Initialize Inputs

clk_10_Mhz = 0;

direction = 0;

enable = 0;

clr = 0;

end

always 

begin

#half_period  clk_10_Mhz = ~clk_10_Mhz; // 100 ns T period

// Wait 100 ns for global reset to finish

end

initial 

begin

#(2 * one_second);

clr = 1;

#(2 * one_second);

clr = 0;

#(1 * one_second);

direction = 0;

enable = 1;

#(10* one_second);

enable  = 0;

// Add stimulus here

//$stop;

end

    initial 

begin

#(20* one_second);

$finish;

end

 

endmodule