Презентація - інтервю для ABB.
WHEN REG IS NOT A FLIP FLOP in Verilog.
Used information:
[1]https://www.researchgate.net/post/Again_what_is_the_difference_between_wire_and_reg_in_Verilog
[2]
http://web.mit.edu/6.111/www/f2007/handouts/L06.pdf
[3]
https://courses.cs.washington.edu/courses/cse370/10wi/pdfs/lectures/15-SeqVerilog.pdf
In my work experience and are lot
of time which I spent on interview I heard this questions or close to him many
times. So let see how it is worked.
As we know reg
is a verilog data type that can be synthesized into either sequential or
combinational logic depending on how you code it.
So lets reviewed
all kinds of organization code. Also we know reg
is used inside
always @( ), and inside brackets we can use two kinds
organization , in first use (posedge clk ) or (negedge clk ) for sequential logic (flip-flop), and second
is (*) or (clk) or (some input signal or wire) or (signal_1 or signal_2 or
signal_3). And inside body of always @(
) which market begin end.
For reg assignments we can use
(=)blocking and (<=)non-blocking assignment , in the next example we used
(posedge clk) and non-blocking assignment.
for example
reg myreg;
always @ (posedge
clk) begin
myreg <= some_input;
end
myreg <= some_input;
end
Assumed this all kinds we can write four
different code combinations :
1.1 In first code example myreg_1...
will be synthesize in FLIP-FLOPs as you can see in Image 1, also I
provided compilation report information
from Xilinx ISE WEB pack Tool.
reg myreg_1,
myreg_2, myreg_3;
always @ (posedge
clk) begin // or (negedge clk)
myreg_1 <= some_input;
myreg_1 <= some_input;
myreg_2 <= some_input;
myreg_3 <= some_input;
end
end
============================================================
* HDL Synthesis *
============================================================
Performing bidirectional port resolution...
Synthesizing Unit <test_code>.
Related source file is "test_code.v".
Register <myreg_2> equivalent to <myreg_1> has been removed
Register <myreg_3> equivalent to <myreg_1> has been removed
Found
1-bit register for signal <myreg_1>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <test_code> synthesized.
============================================================
HDL Synthesis Report
Macro Statistics
# Registers : 1
1-bit
register
: 1
============================================================
============================================================
HDL Synthesis Report
Macro Statistics
# Registers
: 1
1-bit
register
: 1
============================================================
============================================================
* Low Level Synthesis *
============================================================
Optimizing unit <test_code> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on
block test_code, actual ratio is 0.
FlipFlop myreg_1 has been replicated 2 time(s)
to handle iob=true attribute.
Final Macro Processing ...
============================================================
Final Register Report
Macro Statistics
# Registers : 3
Flip-Flops : 3
============================================================
1.2 This kind of code showing how FLIP-FLOP will be connected when we use
assignment result for other assignment Image 2. And this kind of assignment
classical used in design pipeline design or shift registers design.
reg myreg_1,
myreg_2, myreg_3;
always @ (posedge
clk) begin // or (negedge clk)
myreg_1 <= some_input;
myreg_1 <= some_input;
myreg_2 <= myreg_1;
myreg_3 <= myreg_2;
end
end
Image
2.
============================================================
* HDL Synthesis *
============================================================
Performing bidirectional port resolution...
Synthesizing Unit <test_code>.
Related source file is "test_code.v".
Found 1-bit register for signal <myreg_1>.
Found 1-bit register for signal <myreg_2>.
Found 1-bit register for signal <myreg_3>.
Summary:
inferred 3 D-type flip-flop(s).
Unit <test_code> synthesized.
============================================================
HDL Synthesis Report
Macro Statistics
# Registers : 3
1-bit
register : 3
============================================================
============================================================
* Advanced HDL Synthesis *
============================================================
============================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 3
Flip-Flops : 3
============================================================
============================================================
* Low Level Synthesis *
============================================================
Optimizing unit <test_code> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on
block test_code, actual ratio is 0.
FlipFlop myreg_1 has been replicated 1 time(s)
to handle iob=true attribute.
Final Macro Processing ...
Processing Unit <test_code> :
Found
2-bit shift register for signal <myreg_2>.
Unit <test_code> processed.
============================================================
Final Register Report
Macro Statistics
# Registers : 2
Flip-Flops : 2
# Shift Registers : 1
2-bit
shift register
: 1
============================================================
2. This part of code also will be synthesize in FLIP-FLOP logic
reg myreg_1,
myreg_2, myreg_3;
always @ (posedge
clk) begin // or (negedge clk)
myreg_1 = some_input;
myreg_2 = myreg_1;
myreg_1 = some_input;
myreg_2 = myreg_1;
myreg_3 = myreg_2;
end
Image
3
============================================================
* HDL Synthesis *
============================================================
Performing bidirectional port resolution...
Synthesizing Unit <test_code>.
Related source file is "test_code.v".
Register <myreg_2> equivalent to <myreg_1> has been removed
Register <myreg_3> equivalent to <myreg_1> has been removed
Found 1-bit register for signal <myreg_1>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <test_code> synthesized.
============================================================
HDL Synthesis Report
Macro Statistics
# Registers : 1
1-bit
register
: 1
============================================================
============================================================
* Advanced HDL Synthesis *
============================================================
============================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 1
Flip-Flops : 1
============================================================
============================================================
* Low Level Synthesis *
============================================================
Optimizing unit <test_code> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on
block test_code, actual ratio is 0.
FlipFlop myreg_1 has been replicated 2 time(s)
to handle iob=true attribute.
Final Macro Processing ...
============================================================
Final Register Report
Macro Statistics
# Registers : 3
Flip-Flops : 3
============================================================
3.This kind of code will be synthesize
in Combinational Logic !!! Nonblocking assignments do not reflect the
intrinsic behavior of multi-stage combinational logic.!!! Not recommend to use
.
always @(
some_input) // or (*)or (clk) or (signal_1 or signal_2 or signal_3)
begin
if (some_input ==
1'b1)
begin
myreg_1 <=
1'b0;
myreg_2 <=
myreg_1 & some_input;
myreg_3 <=
myreg_2 | myreg_1;
end
else
begin
myreg_1 <=
1'b1;
myreg_2 <=
myreg_1 | some_input;
myreg_3 <=
myreg_2 & myreg_1;
end
end
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "test_code.v"
in library work
Module <test_code> compiled
No errors in compilation
Analysis of file
<"test_code.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module
<test_code> in library <work>.
=========================================================================
*
HDL
Analysis *
=========================================================================
Analyzing top module <test_code>.
Module <test_code> is correct for
synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <test_code>.
Related source file is "test_code.v".
WARNING:Xst:647 - Input <clk> is never
used. This port will be preserved and left unconnected if it belongs to a
top-level block or it belongs to a sub-block and the hierarchy of this
sub-block is preserved.
Unit <test_code> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <test_code> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on
block test_code, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
4. This kind of code will be also synthesize in Combinational Logic and recommend to use. !!! Guideline: use
blocking assignments for combinational always blocks. !!!
always @(
some_input) // or (*) or (clk) or (signal_1 or signal_2 or signal_3)
begin
if (some_input ==
1'b1)
begin
myreg_1 = 1'b0;
myreg_2 = myreg_1
& some_input;
myreg_3 = myreg_2
| myreg_1;
end
else
begin
myreg_1 = 1'b1;
myreg_2 = myreg_1
| some_input;
myreg_3 = myreg_2
& myreg_1;
end
end
end
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